发明名称 低電力スタティックランダムアクセスメモリ
摘要 A bit line driver for a static random access memory (SRAM) cell including: a first voltage supply for supplying a first voltage; a second voltage supply for supplying a second voltage that is less than the first voltage; a write circuit to drive a bit line and an inverse bit line when writing to the SRAM cell; and a pre-charge circuit to pre-charge the bit line and the inverse bit line before reading the content of the SRAM cell. The bit line driver supplies a voltage less than the first voltage by a threshold voltage of one transistor to the bit line or the inverse bit line when the bit line driver drives the bit line or the inverse bit line to a high state.
申请公布号 JP6042999(B2) 申请公布日期 2016.12.14
申请号 JP20150555219 申请日期 2014.01.21
申请人 レイセオン カンパニー 发明人 ミッキー ハリス;ワシム カルド
分类号 G11C11/413;G11C11/412;G11C11/417 主分类号 G11C11/413
代理机构 代理人
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