发明名称 Semiconductor memory tester with fault analysis memory
摘要 The tester includes a fault analysis memory (13) storing faulty data representing test results of a tested random access memory (RAM), etc. The fault analysis memory includes numerous memory blocks (MBLK), whose number equals that of RAMs of high operational rate, which can be tested in a high rate mode. Each block contains numerous banks (BNC), whose number corresponds to path numbers in a shift operation. In a low rate test mode for memories with low operational rate, each bank of each block in the fault analysis memory is described as a region in which faulty data of a simultaneously tested memories are stored. Faulty data of each tested memory are stored in corresponding bank.
申请公布号 DE19812198(A1) 申请公布日期 1998.10.01
申请号 DE19981012198 申请日期 1998.03.19
申请人 ADVANTEST CORP., TOKIO/TOKYO, JP 发明人 SATO, SHINYA, GYODA, SAITAMA, JP;FUJISAKI, KENICHI, GYODA, SAITAMA, JP
分类号 G01R31/28;G01R31/3193;G06F11/22;G11C29/26;G11C29/44;G11C29/56;(IPC1-7):G11C29/00 主分类号 G01R31/28
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