| 发明名称 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE |
| 摘要 |
According to one embodiment, a semiconductor device includes a pair of selection gate transistors arranged on a semiconductor layer, and memory cell transistors arranged on the semiconductor layer between the pair of selection gate transistors. The memory cell transistors are connected to each other in series such that every two adjacent ones of the memory cell transistors share a source/drain region. Further, the memory cell transistors are arranged in an odd number between the pair of selection gate transistors. |
| 申请公布号 |
US2016260724(A1) |
申请公布日期 |
2016.09.08 |
| 申请号 |
US201514733007 |
申请日期 |
2015.06.08 |
| 申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
OHASHI Takashi |
| 分类号 |
H01L27/115 |
主分类号 |
H01L27/115 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor device comprising:
a pair of selection gate transistors arranged on a semiconductor layer; and memory cell transistors arranged on the semiconductor layer between the pair of selection gate transistors, the memory cell transistors being connected to each other in series such that every two adjacent ones of the memory cell transistors share a source/drain region, wherein the memory cell transistors are arranged in an odd number between the pair of selection gate transistors. |
| 地址 |
Minato-ku JP |
