INTEGRATED ELECTRONIC PACKAGE AND STACKED ASSEMBLY THEREOF

摘要

A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.

主权项

1. An integrated electronic package comprising:
a platform segment having a cavity extending through said platform segment, said platform segment having a first surface and a second surface opposing said first surface, said platform segment comprising a semiconductor material; an electronic device residing in said cavity, said electronic device having an active side at which electrical contacts are located and a back side opposing said active side, wherein said active side is approximately coplanar with said first surface of said platform segment; and encapsulation material in said cavity, said encapsulation material coupling said electronic device to said platform segment, wherein said active side of said electronic device is exposed from said encapsulation material and said first and second surfaces of said platform segment are exposed from said encapsulation material.