发明名称 ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL
摘要 A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.
申请公布号 WO2016133683(A1) 申请公布日期 2016.08.25
申请号 WO2016US15988 申请日期 2016.02.01
申请人 QUALCOMM INCORPORATED 发明人 BOSTLEY III, Phil Joseph;SUBRAMANIAM GANASAN, Jaya Prakash
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项
地址
您可能感兴趣的专利