发明名称 SIMULATION APPARATUS, SIMULATION METHOD, AND COMPUTER PRODUCT
摘要 A simulation apparatus includes a generating circuit configured to detect an internal state of a processor at a start of execution of a process block, when among blocks obtained by dividing code of a program executed by the processor that performs out-of-order execution, processing transitions to the process block in a simulation simulating operation in a case where the processor executes the program, the generating circuit being further configured to generate host code that enables calculation of a block execution period for the case where the processor executes the process block, the generating circuit generating the host code by executing the simulation of the process block based on the detected internal state of the processor; and an executing circuit configured to calculate the block execution period by executing the host code generated by the generating circuit.
申请公布号 US2016196156(A1) 申请公布日期 2016.07.07
申请号 US201615070230 申请日期 2016.03.15
申请人 FUJITSU LIMITED 发明人 KUWAMURA Shinya;Ike Atsushi
分类号 G06F9/455 主分类号 G06F9/455
代理机构 代理人
主权项 1. A simulation apparatus comprising: a generating circuit configured to detect an internal state of a processor at a start of execution of a process block, when among blocks obtained by dividing code of a program executed by the processor that performs out-of-order execution, processing transitions to the process block in a simulation simulating operation in a case where the processor executes the program, the generating circuit being further configured to generate host code that enables calculation of a block execution period for the case where the processor executes the process block, the generating circuit generating the host code by executing the simulation of the process block based on the detected internal state of the processor; and an executing circuit configured to calculate the block execution period by executing the host code generated by the generating circuit.
地址 Kawasaki-shi JP