主权项 |
1. A computer implemented method of logic equivalence checking, said method comprising:
accessing a first register-transfer level (RTL) design of an integrated circuit comprising a plurality interconnects, wherein a respective interconnect in said RTL design comprises a first plurality of flip-flops; accessing a first physical implementation of said integrated circuit, wherein said first physical implementation comprises said plurality of interconnects, wherein said respective interconnect in said first physical implementation comprises a second plurality of flip-flops, inverters and buffers; substituting said first plurality of flip-flops with buffers to generate a second RTL design; substituting said second plurality of flip-flops with buffers to generate a second physical implementation; checking logic equivalence between said second RTL design and said second physical implementation; and identifying an logic error in said first physical implantation based on said checking. |