发明名称 Voltage generator circuit and method for controlling thereof
摘要 <p>A voltage generator circuit which is capable of preventing the generation of a through current in a transition to a power-down mode to reduce current consumption. The voltage generator circuit includes a voltage generator (11a) activated by a reference voltage to generate an output voltage. A reference voltage clamp circuit (Tr2; Tr5) is coupled to the voltage generator for clamping the reference voltage to a first voltage in response to a power-down signal to deactivate the voltage generator. An output voltage clamp circuit (Tr3; Tr6) is coupled to the voltage generator for clamping the output voltage to a second voltage. A control circuit (12a; 12b; 12c; 12d) is coupled to the output voltage clamp circuit for enabling the output voltage clamp circuit after the voltage generator is deactivated in response to the power-down signal.</p>
申请公布号 EP1884855(A2) 申请公布日期 2008.02.06
申请号 EP20070118061 申请日期 2002.02.25
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 SATO, HAJIME;SAITO, SYUICHI;IWASE, AKIHIRO
分类号 G05F1/46;G11C5/14 主分类号 G05F1/46
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