| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a synchronous semiconductor device, the power consumption of which is reducible without causing stoppage of an input buffer operation or an internal clock, in response to deactivation of a chip select signal. <P>SOLUTION: The device is equipped with input buffers; a latch signal generating circuit 120 for generating the latch signal CLK1 based on the clock CLK; latch circuits 130 for latching address signal, in response to the latch signal CLK1; delay circuits 140 for supplying the address signal to the latch circuits 130 synchronized with the latch signal CLK1; and NOR gate circuits 150 arranged between the input buffers 110 and the delay circuits 140 to make the address signal activate, in response to the deactivation of the chip select signal CSB. According to the present invention, power consumption generating between the input buffer and the latching circuit is reducible effectively, without having the input buffer operation or the internal clock halted. <P>COPYRIGHT: (C)2009,JPO&INPIT |
