| 摘要 |
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation. |
| 主权项 |
1. A shadow protocol circuit comprising:
(a) a shadow protocol detection circuit having a test data in input, a test clock input, a test mode select input, an enable output, a command output, a command control output, a match input, an address output, and an address control output; (b) a command circuit having a command input connected to the command output, a command control input connected to the command control output, a full pin select output, and a reduced pin select output; and (c) an address circuit including:
i. a shift register having an address input coupled to the address output, an address clock input coupled to the address control output, and a shifted address output;ii. an update register having an input coupled to the shifted address output, an address update input, and an update output;iii. a device address circuit having a device address output; andiv. comparator circuitry having an input coupled to the device address output, an input coupled to the update output, and a match output coupled to the match input. |
