| 摘要 |
A semiconductor memory device for implementing high speed operation of a delay locked loop (DLL) generates internal clock signals synchronized with external clock signals. The semiconductor memory device includes a first input clock buffer for receiving a pair of external clock signals to generate a reference clock signal and a DLL which receives the reference clock signal and a feedback reference clock signal. The respective phases of the reference clock signal and the feedback reference clock signal are compared, and a pair of internal clock signals are generated. The semiconductor memory device further includes a first feedback clock buffer which receives the pair of internal signals and generates a first feedback clock signal, a second feedback clock buffer which receives the pair of internal signals and generates a second feedback clock signal, and a second input clock buffer which receives the first and second feedback clock signals and generates the feedback reference clock signal. The semiconductor memory device utilizes an input clock buffer which receives complementary first and second feedback clock signals, thereby allowing for high-speed operation of the input clock buffer and DLL.
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