PHASE-LOCKED LOOP CIRCUIT

摘要

A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (UDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a linear range after a change in the frequency of said frequency modulated signals (UDIV) to a desired frequency. The lock time of the phase-locked loop circuit is improved without the requirement of complex circuitry.