SRAM array comprising multiple cell cores

摘要

An SRAM array having multiple cell cores to store and retrieve data. A cell core includes a plurality of SRAM cells, and at least two corresponding cell cores build a cell core row. A word decoder is configured to decode incoming address signals. The word decoder includes a cell core select unit configured to generate a cell core row select signal from a combination of a first part of the incoming address signals and a received clock signal.

主权项

1. A static random access memory (SRAM) array comprising:
multiple cell cores to store and retrieve word-wide organized data, wherein a cell core comprises a plurality of SRAM cells, and wherein at least two corresponding cell cores build a cell core row of the SRAM array, the SRAM array including at least two cell core rows, wherein the cell core row is configured to hold multiple storage words; a word decoder configured to decode one or more incoming address signals representing a storage address into a single word line, wherein one storage word uniquely identified by the single word line is activated within the cell core row, the word decoder comprising:
a cell core select unit configured to generate a cell core row select signal activating a decoding element uniquely corresponding to the cell core row based on input of a first part of the one or more incoming address signals and a received clock signal;at least two decoding elements, each decoding element of the at least two decoding elements corresponding to a respective cell core row of the at least two cell core rows and comprising:
a first decoding block for receiving and decoding a second part of the one or more incoming address signals for building an upper portion of one or more word line select signals and a second decoding block for receiving and decoding a third part of the one or more incoming address signals for building a lower portion of the one or more word line select signals; and a respective word line driver for each cell core row of the at least two cell core rows, configured to combine the upper portion of a word line select signal, of the one or more word line select signals, from the first decoding block of the decoding element corresponding to the cell core row and the lower portion of the word line select signal from the second decoding block of the decoding element corresponding to the cell core row to form a unique word line signal per storage address.