SEMICONDUCTOR DEVICE OR ELECTRONIC COMPONENT INCLUDING THE SAME

摘要

Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.

主权项

1. A semiconductor device comprising:
a circuit; and a first memory cell, wherein the circuit includes a first transistor, a second transistor, first to sixth capacitors, first to fourth wirings, a first sense amplifier, and a second sense amplifier, wherein the first sense amplifier includes a first input/output terminal and a second input/output terminal, wherein the second sense amplifier includes a third input/output terminal and a fourth input/output terminal, wherein the first memory cell is over the first sense amplifier and the second sense amplifier, wherein the first wiring is electrically connected to a first electrode of the first capacitor, one of a source and a drain of the first transistor, a first electrode of the fifth capacitor, and the first input/output terminal, wherein the second wiring is electrically connected to a first electrode of the second capacitor, one of a source and a drain of the second transistor, a first electrode of the sixth capacitor, and the second input/output terminal, wherein the third wiring is electrically connected to a first electrode of the third capacitor, the other of the source and the drain of the first transistor, a second electrode of the sixth capacitor, and the third input/output terminal, wherein the fourth wiring is electrically connected to a first electrode of the fourth capacitor, the other of the source and the drain of the second transistor, a second electrode of the fifth capacitor, and the fourth input/output terminal, and wherein the first memory cell is electrically connected to the first wiring.