发明名称 |
PHASE LOCKED LOOP, WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION METHOD |
摘要 |
A phase locked loop has an integer phase detector to detect an integer phase by measuring a cycle number, a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal, a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal, a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal and the frequency error signal, a phase error generator to generate a phase error by integrating an output signal of the glitch corrector, an oscillator controller to control an oscillation frequency of the oscillation signal, and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state, and to stop detection of the integer phase when the phase-lock state is detected. |
申请公布号 |
US2016380759(A1) |
申请公布日期 |
2016.12.29 |
申请号 |
US201615189236 |
申请日期 |
2016.06.22 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
KONDO Satoshi;SAI Akihide;FURUTA Masanori |
分类号 |
H04L7/033 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
1. A phase locked loop comprising:
an integer phase detector to detect an integer phase by measuring a cycle number of at least one of an output signal of an oscillator and an oscillation signal that is a division signal of the output signal; a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal; a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal based on a frequency control signal which controls a frequency of the reference signal, and the integer and fractional phases; a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal when an absolute value of the frequency error signal is equal to or larger than a specific threshold value and to output the frequency error signal when the absolute value of the frequency error signal is smaller than the threshold value; a phase error generator to generate a phase error by integrating an output signal of the glitch corrector by temporal integration; an oscillator controller to control an oscillation frequency of the oscillation signal based on the phase error signal; and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state based on the output signal of the glitch corrector, and to stop detection of the integer phase when the phase-lock state is detected. |
地址 |
Minato-ku JP |