| 发明名称 |
AUDIO PROCESSING APPARATUS |
| 摘要 |
In an audio processing apparatus configured to supply audio data to a processor configured to process audio data, a plurality of receivers, each configured to receive audio data and a work clock carried with the audio data and to supply the audio data to the processor; a plurality of PLL circuits corresponding to the plurality of receivers, each PLL circuit being configured to generate a clock signal based on a word clock received by the corresponding receiver; and a selector configured to select a clock signal from among a plurality of clock signals generated by the plurality of PLL circuits, and to supply the selected clock signal to the processor, the processor outputting the processed audio data at timing synchronized with the selected clock signal are provided. |
| 申请公布号 |
US2016380757(A1) |
申请公布日期 |
2016.12.29 |
| 申请号 |
US201615192688 |
申请日期 |
2016.06.24 |
| 申请人 |
Yamaha Corporation |
发明人 |
AISO Masaru;HASEGAWA Masatoshi |
| 分类号 |
H04L7/033;G06F3/0484;G06F3/16 |
主分类号 |
H04L7/033 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An audio processing apparatus configured to supply audio data to a processor to process the audio data, comprising:
a plurality of receivers, each configured to receive audio data and a work clock carried with the audio data and to supply the audio data to the processor; a plurality of PLL circuits corresponding to the plurality of receivers, each PLL circuit being configured to generate a clock signal based on a word clock received by the corresponding receiver; and a selector configured to select a clock signal from among a plurality of clock signals generated by the plurality of PLL circuits, and to supply the selected clock signal to the processor, the processor outputting the processed audio data at timing synchronized with the selected clock signal. |
| 地址 |
Hamamatsu-shi JP |
