COMPUTER ARCHITECTURE USING RAPIDLY RECONFIGURABLE CIRCUITS AND HIGH-BANDWIDTH MEMORY INTERFACES

摘要

A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions.

主权项

1. A programmable device, comprising:
one or more programming regions, each comprising a plurality of configurable logic blocks, wherein each configurable logic block of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block of the plurality of configurable logic blocks via a programmable interconnect fabric, wherein a first programming region of the one or more programming regions is configured to execute a first instruction in an instruction stream; and configuration logic configured to, in response to a second instruction in the instruction stream, reconfigure hardware in one or more of the plurality of configurable logic blocks in the first programming region independently from any other programming region of the one or more programming regions, wherein the first programming region is configured to execute the second instruction using the reconfigured hardware in the one or more of the plurality of configurable logic blocks in the first programming region.