Processor bridging in heterogeneous computer system

摘要

A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.

主权项

1. In a heterogeneous computer system for executing software having at least one performance processor, an x86 chipset supporting said at least one performance processor for executing tasks of said software and a hypervisor processor consuming less power than said at least one performance processor, said x86 chipset comprising a north bridge, a bridge logic device comprising:
a hypervisor operation logic maintaining status of said system under said at least one performance processor; a processor language translator logic translating between processor languages of said at least one performance and said hypervisor processors; and a high-speed bus switch having first, second and third ports for relaying data across any two of said three ports bidirectionally, wherein said first port is connected to said at least one performance processor via a first front-side bus, said second port is connected to said hypervisor processor via said processor language translator logic and a second front-side bus, and said third port is connected to said north bridge of said x86 chipset via a third front-side bus, wherein said at least one performance processor and said hypervisor processor all access said north bridge via said third front-side bus.