发明名称 APPARATUS OF PARITY INTERLEAVING FOR ENCODING VARIABLE-LENGTH SIGNALING INFORMATION AND METHOD USING THE SAME
摘要 Disclosed are a parity interleaving apparatus for variable length signaling information and a parity interleaving method using the same. According to an embodiment of the present invention, the parity interleaving apparatus comprises a memory and a processor. The processor divides parity bits in an LDPC encoding language having the length of 16200 and an encoding ratio of 3/15 into a plurality of groups, and generates a parity bit string for puncturing parity by group-wise interleaving the groups by using a group-wise interleaving order. The memory supplies the parity bit string for puncturing parity to a parity puncturing unit.
申请公布号 KR20160105311(A) 申请公布日期 2016.09.06
申请号 KR20160020854 申请日期 2016.02.22
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 PARK, SUNG IK;KWON, SUN HYOUNG;LEE, JAE YOUNG;KIM, HEUNG MOOK
分类号 H03M13/27;H03M13/00;H03M13/11 主分类号 H03M13/27
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