OUTPUT CAPACITANCE REDUCTION IN POWER TRANSISTORS

摘要

Technologies are described for reduction of an output capacitance of a transistor. In some examples, spacing of source-to-drain metallization may be increased and a sealed air-gap may be employed in an elongated trench in the drain region to reduce a dielectric constant of a portion of the body region and thereby the output capacitance of the transistor. In other examples, a planar area component of a body-drain junction may be reduced by forming a spherical cavity at a bottom portion of the body-drain junction and sealing the cavity with a low dielectric constant material. In further examples, a sealed cavity may be formed in an epitaxial region below the body region through formation and removal of selective buried oxide islands. In yet other examples, the output capacitance may be reduced through removal of areas in the drain region of the transistor that do not contribute to the current flow.

主权项

1. A semiconductor device, comprising:
a substrate; an epitaxial layer in contact with a surface of the substrate; a nitride layer in contact with a surface of the epitaxial layer; a body region within a top portion of the epitaxial layer; a source region within the top portion of the epitaxial layer, the source region electrically coupled to the body region; and a drain region within the epitaxial layer, wherein the epitaxial layer includes a cavity region below the nitride layer between the drain region and the body region such that a planar drift distance between the drain region and the source region is increased by two or more dimensions of the cavity region.