SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF

摘要

A solid-state imaging device includes a P-well, a gate insulating film, a gate electrode, a P+-type pinning layer that is located in the P-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a P−-type impurity region that is located in the P-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an N−-type impurity region that is in contact with the P−-type impurity region and the gate insulating film, and an N−−-type impurity region that surrounds at least a portion of the N−-type impurity region in plan view.

主权项

1. A solid-state imaging device comprising:
a first conductivity type semiconductor layer; a gate insulating film located on the semiconductor layer; a gate electrode located on the gate insulating film; a first conductivity type first impurity region that is located in the semiconductor layer so as to be outside the gate electrode and start from a first end portion of the gate electrode in plan view; a first conductivity type second impurity region that is located in the semiconductor layer so as to extend under the gate electrode from a first end portion side and be in contact with the first impurity region; a second conductivity type third impurity region that is located in the semiconductor layer so as to extend under the second impurity region and be in contact with the second impurity region and the gate insulating film; a second conductivity type fifth impurity region that is located in the semiconductor layer so as to extend under the first impurity region and the third impurity region and surround at least a portion of the third impurity region in plan view; and a second conductivity type fourth impurity region that is located in the semiconductor layer and includes a portion that is under a second end portion of the gate electrode, wherein the first impurity region, the second impurity region, the third impurity region, and the semiconductor layer are located in the stated order from the outside of the gate electrode on the first end portion side toward the second end portion of the gate electrode in plan view, impurity concentration in the first impurity region, the second impurity region, and the semiconductor layer decreases in the stated order, and impurity concentration in the fifth impurity region is lower than that of the third impurity region.