| 摘要 |
Provided is a relay device in which an interface module 61 relays control signal communication between a main CPU 621, a light source control CPU 651, and a camera head CPU 242. The interface module 61 is provided with: an FPGA 610 comprising CPU interfaces 611 to 613 that correspond to each of the communication methods of each of CPUs 621, 651, 242; and first and second storage units 615 (617), 616 (618). The FPGA 610 relays a control signal between the main CPU 621, the light source control CPU 651, and the camera head CPU 242 at first to third communication timings while temporarily storing said control signal in the first and second storage units 615 (617), 616 (618). In addition, the first communication timing and the second and third communication timings are set to timings that are shifted from each other. |
