| 摘要 |
The invention relates to a method for estimating bandwidth mismatch in a time-interleaved A/D converter (10) comprising
- precharging to a first state second terminals of capacitors (3) in each channel (1) of a plurality of channels and sampling (2) a reference analog input voltage signal (V ref ) applied via a first switchable path (6) whereby the sampled input voltage signal is received at first terminals of said capacitors,
- setting in each channel said second terminals to a second state, thereby generating a further reference voltage signal (V diff ) at said first terminals,
- applying said reference analog input voltage signal to said first terminals via a second switchable path (7), said second path having a given impedance being higher than the known impedance of said first path, thereby creating on said first terminals a non-zero settling error indicative of an incomplete transition from said further reference voltage signal to said reference analog input voltage signal,
- quantizing said settling error, thereby obtaining an estimate of the non-zero settling error in each channel,
- comparing said estimates of said non-zero settling errors of said channels and deriving therefrom an estimation of the bandwidth mismatch. |
