| 摘要 |
PROBLEM TO BE SOLVED: To provide one-bit comparison full adder capable of reducing a circuit scale. SOLUTION: This one-bit comparison full adder 1 is constituted so that a one bit comparator 3 can be composited with a one bit full adder 5, and that at this composition, a semi-adder adding part 2 can be shared by the one-bit comparator 3 and the one-bit full adder 5. In the one bit comparison full adder 1, transistors can be reduced, and a circuit scale can be reduced.
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