发明名称 ERROR DETECTION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME
摘要 An error detection circuit may include a selection unit that sequentially selects a primary data group and a secondary data group according to a first control signal and generates an output signal; a first operation unit that performs an error detection operation on the output signal and outputs a preliminary error operation signal; a storage unit that latches the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit that performs an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit and generates an internal error operation signal; and a comparison unit that compares the internal error operation signal with an external error operation signal and outputs a result of the comparison as an error detection signal.
申请公布号 US2016253228(A1) 申请公布日期 2016.09.01
申请号 US201514711491 申请日期 2015.05.13
申请人 SK hynix Inc. 发明人 CHA Jin Youp;LIM Yu Ri
分类号 G06F11/07 主分类号 G06F11/07
代理机构 代理人
主权项 1. An error detection circuit comprising: a selection unit configured to sequentially select a primary data group and a secondary data group according to a first control signal, and generate an output signal; a first operation unit configured to perform an error detection operation on the output signal of the selection unit, and output a result of the error detection operation as a preliminary error operation signal; a storage unit configured to latch the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit configured to perform an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit, and generate a result of the error detection operation as an internal error operation signal; and a comparison unit configured to compare the internal error operation signal with an external error operation signal, and output a result of the comparison as an error detection signal.
地址 Icheon-si Gyeonggi-do KR