PHYSICAL AWARE TECHNOLOGY MAPPING IN SYNTHESIS

摘要

A method of performing physical aware technology mapping in a logic synthesis phase of design of an integrated circuit and a system to perform physical aware technology mapping are described. The system includes a memory device to store a logic design of the integrated circuit, and a processor to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each latch in a logic design based on an algorithm, to determine a location of each combinational logic gate in the logic design, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.

主权项

1. A system to perform physical aware technology mapping of a logic design to physical components in a logic synthesis phase of design of an integrated circuit, the system comprising:
a memory device configured to store a logic design of the integrated circuit; and a processor configured to subdivide a core area representing a sub-block of the integrated circuit into equal-sized grids, the core area including one or more input ports and one or more output ports, to determine a location of each of one or more latches in a logic design based on an algorithm, to determine a location of each of one or more combinational logic gates in the logic design based on the locations of the one or more latches, the one or more input ports, or the one or more output ports, and to obtain the technology mapping based on the locations of the one or more latches, the locations of the one or more combinational logic gates, and associated path delays.