REDUCING ERRORS DUE TO NON-LINEARITIES CAUSED BY A PHASE FREQUENCY DETECTOR OF A PHASE LOCKED LOOP

摘要

A phase frequency detector (PFD) includes a first circuit portion and a second circuit portion. The first circuit portion receives a reference signal and activates a first error signal if the phase of the reference frequency leads the phase of a feedback signal. The second circuit portion receives the reference and activates a second error signal if the phase of the reference frequency lags the phase of the feedback signal. The first circuit portion is powered by a first power supply, and the second circuit portion is powered by a second power supply. A PLL implemented using the PFD generates a frequency output with minimized jitter.

主权项

1. A phase frequency detector (PFD) comprising:
a first circuit portion to receive a reference signal (Fret) and to activate a first error signal (UP) if the phase of said reference frequency (Free leads the phase of a feedback signal (Ffb); and a second circuit portion to receive said feedback signal (Ffb) and to activate a second error signal (DOWN) if the phase of said reference frequency (Fref) lags the phase of said feedback signal (Ffb), wherein said first circuit portion is powered by a first power supply, and wherein said second circuit portion is powered by a second power supply, wherein said first power supply is different from said second power supply.