发明名称 FLUSHING AND RESTORING CORE MEMORY CONTENT TO EXTERNAL MEMORY
摘要 A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.
申请公布号 US2016378660(A1) 申请公布日期 2016.12.29
申请号 US201514751889 申请日期 2015.06.26
申请人 Intel Corporation 发明人 Gendler Alexander;Berkovits Ariel;Mishaeli Michael;Shulman Nadav;Desai Sameer;Rehana Shani;Anati Ittai;Shafi Hisham
分类号 G06F12/08;G11C11/406;G06F1/32;G11C7/10 主分类号 G06F12/08
代理机构 代理人
主权项 1. An integrated circuit (IC) comprising: a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.
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