发明名称 Checkerboard buffer using memory blocks
摘要 Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices, and where data is stored according to the first order using blocks of memory locations, each block having a number of memory locations equal to a power of 2; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
申请公布号 US2002109698(A1) 申请公布日期 2002.08.15
申请号 US20010907854 申请日期 2001.07.17
申请人 CHAMPION MARK;DOCKTER BRIAN 发明人 CHAMPION MARK;DOCKTER BRIAN
分类号 G06T1/60;G09G3/00;G09G3/34;G09G5/39;G09G5/391;G09G5/393;G09G5/395;G09G5/399;G11C7/10;H04N5/14;H04N5/44;H04N5/46;H04N5/74;H04N7/01;(IPC1-7):G09G5/36 主分类号 G06T1/60
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