| 摘要 |
A data driving circuit and a delay locked loop are provided to prevent the delay locked loop from being unlocked by limiting a length of a phase difference signal. A delay locked loop includes a phase detector(21), and a delay line(23). The phase detector outputs a phase difference signal in response to at least one delay signal, a first clock signal and a second clock signal. The phase difference signal has a phase difference value between the first clock signal and the second clock signal in response to the first clock signal or the second clock signal. The phase difference signal has no phase difference value in response to the delay signal. The delay line obtains at least one delay signal and the second clock signal by delaying the first clock signal. A first delay as a delay of the second clock signal for the first clock signal is changed in response to the phase difference signal.
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