| 摘要 |
<p>An LDMOS device securing wide silicon region is provided to enhance break-down voltage of a device and reduce on-resistance by forming additional p on the surface of the STI. In a LDMOS device securing wide silicon region, a first conductive first well(121) is formed on the second conductive board(110). A plurality of element isolation films(150) is formed within the first conductivity type first well. The second conductive ion implantation region(140) is formed on the surface of the element isolation film. The gate(160) is selectively formed on the first conductive first well and element isolation film, and a drain and source is formed in both sides of a gate. In the structure of the LDMOS device using the STI process, the break down voltage of device is increased and on-resistance is decreased by forming the additional P-type domain, the second conductive type ion implantation region, on the STI surface.</p> |
