发明名称 Techniques for trench isolation using flowable dielectric materials
摘要 Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.
申请公布号 US9406547(B2) 申请公布日期 2016.08.02
申请号 US201314139964 申请日期 2013.12.24
申请人 INTEL CORPORATION 发明人 Jhaveri Ritesh;Luce Jeanne L.;Park Sang-Won;Hanken Dennis G.
分类号 H01L21/76;H01L21/762;H01L29/06;H01L29/78;H01L29/66 主分类号 H01L21/76
代理机构 Finch & Maloney PLLC 代理人 Finch & Maloney PLLC
主权项 1. A method of forming an integrated circuit, the method comprising: depositing a flowable dielectric over a semiconductive substrate having first and second semiconductive fins extending from an upper surface thereof and a trench formed between the first and second semiconductive fins, wherein the trench has a width less than or equal to about 30 nm; curing the flowable dielectric to form a dielectric layer over the semiconductive substrate, wherein the dielectric layer resides, at least in part, within the trench; and treating the dielectric layer to modify at least one of its dielectric properties, density, and etch rate, wherein treating the dielectric layer comprises applying a thermal treatment that utilizes a furnace-based, vertical directional solidification (VDS) process in which the dielectric layer is subjected to an environment of about 90% steam or greater for a first period of time at a first temperature in the range of about 180-240° C. and for a second period of time at a second temperature in the range of about 450-525° C.
地址 Santa Clara CA US