发明名称 Memory apparatus with multi-level cells and operation method thereof
摘要 A memory apparatus and an operation method thereof are provided. The memory apparatus includes a plurality of multi-level cells and a controller. The controller encodes input data according to a target encoding code to generate a plurality of encoded subsets, and stores the encoded subsets into the multi-level cells. Thereafter, the controller could read data from the multi-level cells, perform an error correction procedure on the read data to correct and recover the read data as recovered data, and decode the recovered data according to the target encoding code. Consequently, sensing windows between threshold voltage distributions of the multi-level cells are expanded.
申请公布号 US8386884(B2) 申请公布日期 2013.02.26
申请号 US20090502353 申请日期 2009.07.14
申请人 MACRONIX INTERNATIONAL CO., LTD.;CHEN CHUNG-KUANG 发明人 CHEN CHUNG-KUANG
分类号 G11C29/00;G11C11/34 主分类号 G11C29/00
代理机构 代理人
主权项
地址