Coreless layer buildup structure with LGA and joining layer

摘要

A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.

主权项

1. A substrate for use in a PC board comprising:
a) a resin-coated, Cu-based, coreless buildup layer, said coreless buildup layer comprising at least one of the elements: filled epoxy and filled PPE; b) a first metal layer disposed on said coreless buildup layer; c) an LGA electrically connected to said first metal layer; and d) at least two joining layers comprising 3D-micro arrays comprising nubs with partially cured adhesives formulated from controlled sized particles ranging from a nanometer scale to a micro meter scale, at least one of said at least two joining layers connecting multiple signal layers having a high dielectric constant-based embedded electrical components chosen from the group: capacitors and resistors with resistance ranges from 15 ohms to 30,000 ohms and having pad diameter ranges from 5 μm to 250 μm for internal and external interconnect applications, and at least one other of said at least two joining layers connecting said signal layer and said coreless buildup layer having pad diameter ranges from 5 μm to 250 μm for internal and external interconnect applications.