发明名称 |
System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions |
摘要 |
Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit. |
申请公布号 |
US2016350221(A1) |
申请公布日期 |
2016.12.01 |
申请号 |
US201615232551 |
申请日期 |
2016.08.09 |
申请人 |
Intel Corporation |
发明人 |
Shaikh Omar M.;Rajwar Ravi;Caprioli Paul;Al-Otoom Muawya M. |
分类号 |
G06F12/0817;G06F12/0875 |
主分类号 |
G06F12/0817 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
execution circuitry to execute each instruction of a transaction; a buffer to maintain a mapping from architectural registers to physical registers, wherein the buffer to maintain a plurality of register checkpoints for a plurality of transactional memory (TM) regions by tracking indicators between TM regions to identify a position in the buffer of the last committed instruction and identify a boundary between a youngest TM region and a currently retiring instruction position; a data cache to store data associated with executed instructions, wherein each entry of the data cache has a bit per TM region indicator to mark memory state of speculative reads wherein a read-bit for a TM region is set when data is speculatively read from that cache line during that transaction and a write-bit is set to indicate when the cache line has speculatively written data. |
地址 |
Santa Clara CA US |