<p>PURPOSE: A semiconductor memory device is provided to implement high integration by vertically arranging a variable resistance pattern on an active pattern. CONSTITUTION: A plurality of active patterns are arranged on a substrate(100). The active pattern includes a first dopant region(105a), a channel region(103a), and a second dopant region(105b) which are vertically stacked. The channel region is formed between the first dopant region and the second dopant region. A gate pattern(120a) is formed on one sidewall of the active pattern. A gate dielectric pattern(110a) is formed between the gate pattern and the active pattern. A word line is connected to the gate pattern which is arranged in each row. A conductive pattern(120b) is formed on the other sidewall of the active pattern.</p>
申请公布号
KR20130027155(A)
申请公布日期
2013.03.15
申请号
KR20110090545
申请日期
2011.09.07
申请人
SAMSUNG ELECTRONICS CO., LTD.
发明人
KIM, SU A;PARK, CHUL WOO;KIM, JIN HO;HWANG, HONG SUN;LEE, SANG BO