| 摘要 |
The present invention provides a CMOS SRAM cell comprising two cross-coupled inverters each comprising a pmos and an nmos transistor, a first signal line connected to the sources of each of the nmos transistors, a second signal line, parallel to the first signal line, and connected to the source of one of said pmos transistors, and a third signal line connected to the source of the other of said pmos transistors, wherein the third signal line is orthogonally connected to the first and second signal lines. The present invention also provides a CMOS SRAM cell comprising two cross-coupled inverters, a pair of bitlines for writing data to the cell, and at least one further bitline for reading data from the cell. |
