PHASE GENERATOR BASED ON DELAY LOCK LOOP CIRCUIT AND DELAY LOCKING METHOD THEREOF
摘要
The present invention relates to a phase generator based on a delay locked loop circuit and a phase generating method capable of preventing locking errors while realizing broadband by placing a delay timing on an optimal band depending on the result of comparing an input clock and an output clock. The phase generator comprises: a delay control unit for producing and outputting an oscillating control voltage based on the result of comparing a phase of an outer standard clock and feedback clock signals to the frequency; a course setting unit for setting a band region for locking errors based on preventing conditions; a regulator for adjusting a set voltage level corresponding to the band region of the course setting unit and outputting the same; and a voltage control delay line for converting and outputting a phase of at least one output clock and a voltage level based on the set voltage of the regulator and control voltage of the delay control unit.
申请公布号
KR101628160(B1)
申请公布日期
2016.06.09
申请号
KR20140194798
申请日期
2014.12.31
申请人
UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)