NANOWIRE FIELD EFFECT TRANSISTOR WITH INNER AND OUTER GATES

摘要

A semiconductor device comprising a suspended semiconductor nanowire inner gate and outer gate. A first epitaxial dielectric layer surrounds a nanowire inner gate. The first epitaxial dielectric layer is surrounded by an epitaxial semiconductor channel. The epitaxial semiconductor channel surrounds a second dielectric layer. A gate conductor surrounds the second dielectric layer. The gate conductor is patterned into a gate line and defines a channel region overlapping the gate line. The semiconductor device contains source and drain regions adjacent to the gate line.

主权项

1. A method of forming a semiconductor structure comprising:
etching a trench region in a substrate layer, wherein the trench region is along a first length of the substrate layer; forming a nanowire layer directly above the substrate layer along a width of the substrate layer and in mechanical contact with a top surface of the substrate layer except above the trench region, wherein a width of the nanowire layer above the trench region is less than a width of portions of the nanowire in mechanical contact with the top surface of the substrate layer; and forming a gate structure having a bottom surface directly above and in mechanical contact with the top surface of the substrate layer in a portion of the trench region, wherein a length of the gate structure is substantially parallel to the first length of the substrate layer, and wherein the gate structure surrounds a first surface of the nanowire layer corresponding to an outer surface of a portion of the nanowire layer above the trench region, and wherein the gate structure comprises (i) an inner gate dielectric layer having an inner surface surrounding the first surface of the nanowire layer, (ii) a channel layer having an inner surface surrounding an outer surface of the inner gate dielectric layer, (iii) an outer gate dielectric layer having an inner surface surrounding an outer surface of the channel layer, (iv) an outer gate electrode having an inner surface surrounding an outer surface of the first outer gate dielectric layer, and (v) a second outer gate dielectric layer directly below and in mechanical contact with a bottom surface of the outer gate electrode, wherein a bottom surface of the second outer gate layer is in mechanical contact with the top surface of the substrate layer.