Apparatus and method for optimizing the number of accesses to page-reference count storage in page link list based switches

摘要

A packet processor includes a packet memory manager configured to receive a single header reference count and a single payload reference count for a packet. A page link list walk for the header under the control of the header reference count is performed in parallel with a page link list walk for the payload under the control of the payload reference count.

主权项

1. A packet processor, comprising:
a packet memory manager configured to
receive a single header reference count and a single payload reference count for a packet with a header and a payload; andperform in parallel a page link list walk for the header under the control of the single header reference count and a page link list walk for the payload under the control of the single payload reference count, wherein each page link list walk traverses a linked list of all pages that a particular packet uses in packet memory.