SAMPLING NETWORK AND CLOCKING SCHEME FOR A SWITCHED-CAPACITOR INTEGRATOR

摘要

Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.

主权项

1. A switched-capacitor integrator, comprising:
an amplifier having first and second output nodes and first and second input nodes; a first integration capacitor coupled between the first output node and the first input node of the amplifier; a second integration capacitor coupled between the second output node and the second input node of the amplifier; first and second sampling capacitors, each having a first terminal and a second terminal; a first set of switches configured, during a first sampling phase of the integrator, to connect first and second voltages of a differential signal with the first terminals of the first and second sampling capacitors, respectively; a second set of switches configured to connect the second terminals of the first and second sampling capacitors with a reference potential during the first sampling phase of the integrator, wherein a switching frequency of the first set of switches is less than a switching frequency of the second set of switches; and a third set of switches configured, during a first integration phase of the integrator, to connect the second terminals of the first and second sampling capacitors with the first and second input nodes of the amplifier, respectively.