| 摘要 |
<p>A flash memory device and a manufacturing method thereof are provided to reduce the size of a cell transistor and to restrain the generation of a short channel effect by using an improved gate electrode structure of a spacer type. An active region is defined on a semiconductor substrate(50). A source region is formed within the active region. A recess region is formed at both sides of the source region. Floating gates(64) are formed at sidewalls of the recess region via a tunnel insulating layer. A source line(58) is formed on the source region. The source line crosses the active region. A control gate electrode(68) is formed at both sidewalls of the source line. The control gate crosses the active region including the floating gate. An inter-gate dielectric(66) is interposed between the control gate electrode, the floating gate, and the source line. A drain region is formed within the active region in order to be aligned with the control gate electrode.</p> |
