发明名称 |
POOLED MEMORY ADDRESS TRANSLATION |
摘要 |
A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request. |
申请公布号 |
US2016283399(A1) |
申请公布日期 |
2016.09.29 |
申请号 |
US201514671566 |
申请日期 |
2015.03.27 |
申请人 |
Intel Corporation |
发明人 |
Das Sharma Debendra |
分类号 |
G06F12/10;G06F13/42;G06F13/40 |
主分类号 |
G06F12/10 |
代理机构 |
|
代理人 |
|
主权项 |
1. An apparatus comprising:
a first shared memory controller comprising:
a first interface to receive, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool, wherein the request includes a node address according to an address map of the computing node;translation logic to use an address translation structure to translate the first address into a corresponding second address according to a global address map for the memory pool;routing logic to:
determine that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map; andcause the particular shared memory controller to handle the request. |
地址 |
Santa Clara CA US |