MULTIFUNCTIONAL HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT

摘要

A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

主权项

1. A computer program product for executing a hexadecimal floating point instruction in a computer system, the computer system comprising a plurality of general registers, and a general purpose processor in communications with a computer memory, the processor comprising one or more execution units, the execution units executing instructions fetched from the computer memory, the computer program product comprising:
a computer readable storage medium readable by said computer system, said computer readable storage medium storing instructions for performing fetching a hexadecimal floating point instruction; determining that the hexadecimal floating point instruction is a multiply and add instruction; and responsive to the determining
fetching a first operand comprising a first exponent value and a first fraction and a second operand comprising a second exponent value and a second fraction;multiplying the first fraction value and second fraction value to produce a full precision result;fetching a third operand comprising a third exponent and a third fraction value; and
adding the third operand to the full precision result to produce a second result.