发明名称 VIDEO SIGNAL PROCESSOR, PROCESSING METHOD AND PROGRAM OR RECORDING MEDIUM
摘要 <p><P>PROBLEM TO BE SOLVED: To detect a block boundary accurately without varying the phase of a clock. <P>SOLUTION: A differential signal generator 101 delivers the absolute differentiation value of an inputted video signal to adders 124-0 to 124-15 through a selector 123. Based on the count of horizontal sync signal from a 4 bit counter 122, the selector 123 adds the absolute differentiation values of 16 lines through the adders 124-0 to 124-15. A maximum value detector 131 detects four maximum values of the adders 124-0 to 124-15 sequentially from the larger one, and a decision section 132 makes a decision whether a block boundary exists or not based on the period of the four maximum values. The processor and the method are applicable to a television receiver. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007243417(A) 申请公布日期 2007.09.20
申请号 JP20060061045 申请日期 2006.03.07
申请人 SONY CORP 发明人 UEJIMA ATSUSHI
分类号 H04N5/21;H04N19/00;H04N19/625;H04N19/86 主分类号 H04N5/21
代理机构 代理人
主权项
地址