| 摘要 |
<p>A process for fabricating an electronic integrated circuit comprising a multi¬ layer interconnect stack. A structure (26), such as a MIM capacitor is formed by means of a process that requires the generation of a localized voltage across a nearby primary interconnect line (36) to the substrate. A secondary interconnect path (42) is provided which intersects with the primary interconnect line (36), which is removed after the structure (26) has been formed, so as to create an open circuit in the primary interconnect line (36). Thus, the performance of the circuit is enhanced.</p> |
