| 摘要 |
PROBLEM TO BE SOLVED: To provide bus clock frequency scaling for a bus interconnect and related devices, systems and methods.SOLUTION: The bus interconnect comprises an interconnect network configurable to connect master ports to slave ports. A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic and scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master ports and/or the slave ports meets respective bandwidth conditions, and/or if the latency of the master ports meets respective latency conditions for the master ports. The master ports and/or slave ports can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.SELECTED DRAWING: Figure 1 |
