发明名称 |
MECHANISM TO PRECLUDE I/O-DEPENDENT LOAD REPLAYS IN OUT-OF-ORDER PROCESSOR |
摘要 |
An apparatus includes first and second reservation stations. The first reservation station (421.L) dispatches a load micro instruction, and indicates on a hold bus (444) if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station (421.1-421.N) is coupled to the hold bus (444), and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus (444) that the load micro instruction is the specified load micro instruction, the second reservation station (421.1-421.N) is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources. |
申请公布号 |
WO2016097796(A1) |
申请公布日期 |
2016.06.23 |
申请号 |
WO2014IB03177 |
申请日期 |
2014.12.14 |
申请人 |
VIA ALLIANCE SEMICONDUCTOR CO., LTD. |
发明人 |
COL, GERARD, M.;EDDY, COLIN;HENRY, G., GLENN |
分类号 |
G06F15/163 |
主分类号 |
G06F15/163 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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