| 主权项 |
1. An information processing device, comprising:
a plurality of barrier banks; and one or more processors including at least one of the plurality of barrier banks, wherein each of the plurality of barrier banks comprises
one or more hardware threads configured to execute a thread, anda barrier synchronization mechanism configured to perform barrier synchronization of the plurality of barrier banks, the barrier synchronization mechanism comprises
a shared unit comprising a barrier state indicating whether or not the synchronization is complete,a bottom unit comprising a bitmap indicating that each of the one or more hardware threads has arrived at a synchronization point, anda top unit comprising a non-arrival counter indicating the number of barrier banks yet to be synchronized among the plurality of barrier banks for which barrier synchronization is to be performed, the bottom unit checks the bitmap, and notifies a barrier bank specified using target information, and mask information which is information for specifying a position of a don't-care bit for the target information of bottom unit synchronization completion when all the one or more hardware threads have arrived at a barrier synchronization point, the non-arrival counter decrements a value of the non-arrival counter by 1 upon receipt of the bottom unit synchronization completion, and the top unit sets the barrier state to a value indicating synchronization completion when the non-arrival counter decrements to 0. |
