发明名称 Instruction-issuance controlling device and instruction-issuance controlling method
摘要 In a multithread processor capable of executing a plurality of threads, in order to select a thread and instruction for increasing a throughput of the multithread processor, an instruction-issuance controlling device included in the multithread processor includes a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state; a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution; and an instruction-issuance controlling unit configured to perform controlling so that simultaneously issuable instructions are issued from among the selected thread.
申请公布号 US9436464(B2) 申请公布日期 2016.09.06
申请号 US201213692141 申请日期 2012.12.03
申请人 SOCIONECT INC. 发明人 Yamana Tomohiro
分类号 G06F9/30;G06F15/00;G06F9/38 主分类号 G06F9/30
代理机构 Wenderoth, Lind & Ponack, L.L.P. 代理人 Wenderoth, Lind & Ponack, L.L.P.
主权项 1. An instruction-issuance controlling device included in a multithread processor, the device comprising: a resource management unit configured to manage stall information indicating whether or not each of threads in execution is in a stalled state; a thread selection unit configured to select a thread which is not in the stalled state among the threads in execution; and an instruction-issuance controlling unit configured to control the multithread processor so that simultaneously issuable instructions are issued from the selected thread, wherein the resource management unit is configured to, for each of the threads in execution, (i) manage the number of stalled cycles which indicates the number of remaining cycles for the stalled state to determine whether or not the number of the stalled cycles is one or more, and (ii) determine that the thread is not in the stalled state and update the stall information if the number of the stalled cycles is 0.
地址 Kanagawa JP